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Features
* Industry-standard Architecture
- Emulates Many 24-pin PALs(R) - Low-cost Easy-to-use Software Tools * High-speed Electrically-erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-pin Delay * Several Power Saving Options Device ATF20V8B ATF20V8BQ ATF20V8BQL ICC, Standby 50 mA 35 mA 5 mA ICC, Active 55 mA 40 mA 20 mA
* CMOS and TTL Compatible Inputs and Outputs * Input and I/O Pull-up Resistors * Advanced Flash Technology *
- Reprogrammable - 100% Tested High-reliability CMOS Process - 20 Year Data Retention - 100 Erase/Write Cycles - 2,000V ESD Protection - 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts PCI-Compliant Green Package Options (Pb/Halide-free/RoHS Complant) Available
Highperformance EE PLD ATF20V8B ATF20V8BQ ATF20V8BQL
* * * *
Block Diagram
Pin Configurations
All Pinouts Top View
Pin Name CLK I I/O OE * VCC Function Clock Logic Inputs Bi-directional Buffers Output Enable No Internal Connection +5V Supply
CLK/IN IN IN IN IN IN IN IN IN IN IN GND
TSSOP
CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC IN I/O I/O I/O I/O I/O I/O I/O I/O IN OE/IN
DIP/SOIC
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC IN I/O I/O I/O I/O I/O I/O I/O I/O IN OE/IN
PLCC
IN IN CLK/IN * VCC IN I/O 4 3 2 1 28 27 26 IN IN IN * IN IN IN 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O I/O * I/O I/O I/O
IN IN GND * OE/IN IN I/O
12 13 14 15 16 17 18
Rev. 0407J-07/06
1
Description
The ATF20V8B is a high-performance CMOS (electricallyerasable) programmable logic device (PLD) that utilizes Atmel's proven electrically-erasable Flash memory technology. Speeds down to 7.5 ns and power dissipation as low as 10 mA are offered. All speed ranges are specified over the full 5V 10% range for industrial temperature ranges, and 5V 5% for commercial temperature ranges. Several low-power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. The ATF20V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 20R8 family and most 24-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is VCC + 0.75V DC which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial Operating Temperature (Ambient) VCC Power Supply 0C - 70C 5V 5% Industrial -40C - 85C 5V 10%
2
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
DC Characteristics
Symbol IIL IIH Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Condition 0 VIN VIL(Max) 3.5 VIN VCC Com. B-7, -10 Ind. B-15 B-15 Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open B-25 B-25 BQ-10 BQL-15 BQL-15 BQL-25 BQL-25 B-7, -10 Ind. B-15 B-15 Clocked Power Supply Current VCC = Max, Outputs Open, f = 15 MHz B-25 B-25 BQ-10 BQL-15 BQL-15 BQL-25 BQL-25 IOS(1) VIL VIH VOL Output Short Circuit Current Input Low Voltage Input High Voltage VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOL = 24 mA IOL = 16 mA IOH = -4.0 mA 2.4 Com., Ind. VOUT = 0.5V -0.5 2.0 Com. Ind. Com. Ind. Com. Com. Ind. Com. Ind. 80 60 60 60 60 40 20 20 20 20 125 90 105 90 105 55 35 40 35 40 -130 0.8 VCC + 0.75 0.5 0.5 mA mA mA mA mA mA mA mA mA mA mA V V V V V Com. Ind. Com. Ind. Com. Com. Ind. Com. Ind. Com. 60 60 60 60 60 35 5 5 5 5 80 100 80 90 80 90 55 10 15 10 15 110 mA mA mA mA mA mA mA mA mA mA mA 60 Min Typ -35 Max -100 10 90 Units A A mA
ICC
ICC2
Output Low Voltage
VOH Notes:
Output High Voltage
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
3
AC Waveforms(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics(1)
-7 Symbol tPD tCF tCO tS tH tP tW Parameter Input or Feedback to Non-Registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) fMAX Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) tEA tER tPZX tPXZ Note: 1. 2. 3. Input to Output Enable -- Product Term Input to Output Disable --Product Term OE pin to Output Enable OE pin to Output Disable 3 2 2 1.5 2 5 0 8 4 100 125 125 9 9 6 6 3 2 2 1.5 8 outputs switching 1 output switching Min 3 Max 7.5 7 3 5 2 7.5 0 12 6 68 74 83 10 10 10 10 3 2 2 1.5 6 7 2 12 0 16 8 45 50 62 15 15 15 15 3 2 2 1.5 8 10 2 15 0 24 12 37 40 41 20 20 20 20 10 12 Min 3 -10 Max 10 Min 3 -15 Max 15 Min 3 -25 Max 25 Units ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
See ordering information for valid part numbers and speed grades. Shaded -25 parts are obsolete with a last-time buy date of August 19, 1999. Shaded -7 and -15 parts are obsolete with a last-time buy date of September 30, 2006.
4
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Input Test Waveforms and Measurement Levels Output Test Loads
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ CIN COUT Note: 5 6 Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF20V8Bs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR.
Parameter tPR VRST
Description Power-up Reset Time Power-up Reset Voltage
Typ 600 3.8
Max 1,000 4.5
Units ns V
Preload of Registered Outputs
The ATF16V8B's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF20V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate.
Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. For further information, see the Configurable Logic Databook, section titled, "CMOS PLD Programming Hardware and Software Support."
5
Input and I/O Pull-ups
All ATF20V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to V CC . This ensures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below).
Input Diagram
I/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the ATF20V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF20V8B can be configured in one of three different modes. Each mode makes the ATF20V8B look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control. The ATF20V8B universal architecture can be programmed to emulate many 24-pin PAL devices. These architectural subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF20V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the content of the ATF20V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse.
6
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Compiler Mode Selection
Registered ABEL, Atmel-ABEL CUPL LOG/iC OrCAD-PLD PLDesigner Tango-PLD Note: P20V8R G20V8MS GAL20V8_R "Registered" P20V8 G20V8
(1)
Complex P20V8C G20V8MA GAL20V8_C7 "Complex" P20V8 G20V8
(1)
Simple P20V8 G20V8 GAL20V8_C8 "Simple" P20V8 G20V8
(1)
Auto Select P20V8 G20V8A GAL20V8 GAL20V8 P20V8 G20V8
1. Only applicable for version 3.4 or lower.
ATF20V8B Registered Mode
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more registers are required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 20R8 20RP8 20R6 20RP6 20R4 20RP4
Registered Mode Operation
7
Registered Mode Logic Diagram
8
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
ATF20V8B Complex Mode
PAL Device Emulation/PAL Replacement. In the complex Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 20L8 20H8 20P8
Complex Mode Operation
ATF20V8B Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can be emulated using this mode: 14L8 14H8 14P8 16L6 18H6 16P6 18L4 18H4 18P4 20L2 20H2 20P2
Simple Mode Option
9
Complex Mode Logic Diagram
10
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Simple Mode Logic Diagram
11
12
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
13
14
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
ATF20V8B Ordering Information
tPD (ns) 7.5 tS (ns) 5 tCO (ns) 5 Ordering Code ATF20V8B-7JC ATF20V8B-7PC ATF20V8B-7SC ATF20V8B-7XC ATF20V8B-10JC ATF20V8B-10PC ATF20V8B-10SC ATF20V8B-10XC ATF20V8B-10JI ATF20V8B-10PI ATF20V8B-10SI ATF20V8B-10XI 15 12 10 ATF20V8B-15JC ATF20V8B-15PC ATF20V8B-15SC ATF20V8B-15XC ATF20V8B-15JI ATF20V8B-15PI ATF20V8B-15SI ATF20V8B-15XI Note: Package 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0C to 70C)
10
7.5
7
Commercial (0C to 70C)
Industrial (-40C to 85C)
Commercial (0C to 70C)
Industrial (-40C to 85C)
1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
ATF20V8B Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns) 10 tS (ns) 7.5 tCO (ns) 7 Ordering Code ATF20V8B-10JU ATF20V8B-10PU Package 28J 24P3 Operation Range Industrial (-40C to 85C)
Using "C" Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the "I" to the "C" device (7 ns "C" = 10 ns "I") and de-rate power by 30%.
Package Type 28J 24P3 24S 24X 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC) 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
15
ATF20V8BQ and ATF20V8BQL Ordering Information
tPD (ns) 10 tS (ns) 7.5 tCO (ns) 7 Ordering Code ATF20V8BQ-10JC ATF20V8BQ-10PC ATF20V8BQ-10XC ATF20V8BQL-15JC ATF20V8BQL-15PC ATF20V8BQL-15SC ATF20V8BQL-15XC ATF20V8BQL-15JI ATF20V8BQL-15PI ATF20V8BQL-15SI ATF20V8BQL-15XI Package 28J 24P3 24X 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0C to 70C) Commercial (0C to 70C)
15
12
10
15
12
10
Industrial (-40C to 85C))
Note:
1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
ATF20V8BQL Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns) 15 Note: tS (ns) 12 tCO (ns) 10 Ordering Code ATF20V8BQL-15JU ATF20V8BQL-15PU Package 28J 24P3 Operation Range Industrial (-40C to 85C))
1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
Using "C" Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the "I" to the "C" device (7 ns "C" = 10 ns "I") and de-rate power by 30%.
Package Type 28J 24P3 24S 24X 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC) 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
16
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Packaging Information
28J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 12.319 11.430 12.319 11.430 9.906 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 12.573 11.582 12.573 11.582 10.922 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 28J REV. B
R
17
24P3 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 31.623 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 32.131 8.255 7.112 0.559 1.651 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
6/1/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 24P3 REV. D
R
18
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
24S - SOIC
B
D1
PIN 1 ID PIN 1
D
e
E A
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN - 0.10 10.00 7.40 15.20 0.33 0.40 0.23 NOM - - - - - - - - 1.27 BSC MAX 2.65 0.30 10.65 7.60 15.60 0.51 1.27 0.32 NOTE
A1
A A1 D D1
0 ~ 8
L1
E B L
L
L1 e
06/17/2002 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 24S REV. B
R
19
24X - TSSOP
Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007)
4.48(0.176) 4.30(0.169)
6.50(0.256) 6.25(0.246)
PIN 1 0.65(0.0256)BSC
7.90(0.311) 7.70(0.303) 1.20(0.047)MAX
0.15(0.006) 0.05(0.002)
0 ~ 8
0.20(0.008) 0.09(0.004) 0.75(0.030) 0.45(0.018)
04/11/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 24X REV. A
R
20
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Revision History
Revision Level - Release Date J - July 2006 History Ordering Information tables updated to reflect obsolete parts.
21
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0407J-07/06

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